Adjustable dummy fill

ABSTRACT

A method of placing a dummy fill layer on a substrate is disclosed (FIG.  2 ). The method includes identifying a sub-region of the substrate ( 210 ). A density of a layer in the sub-region is determined ( 212 ). A pattern of the dummy fill layer is selected to produce a predetermined density ( 216 ). The selected pattern is placed in the subregion ( 208 ).

CLAIM TO PRIORITY OF NONPROVISIONAL APPLICATION

This application is a divisional of U.S. application Ser. No. 14/230,847filed Mar. 31, 2014, which is a divisional of U.S. application Ser. No.12/883,741 filed Sep. 16, 2010 which is a divisional of U.S. applicationSer. No. 12/460,602 filed Jul. 21, 2009, which claims the benefit ofunder 35 U.S.C. §119(e) of Provisional Application No. 61/088,212, filedAug. 12, 2008, and to Provisional Application No. 61/091,937, filed Aug.26, 2008, the contents of all are incorporated herein by reference.

BACKGROUND OF THE INVENTION

Embodiments of the present invention relate to calculation and placementof an adjustable dummy fill layer to improve semiconductor integratedcircuit processing.

Shrinking semiconductor integrated circuit feature sizes have placedincreasing challenges on semiconductor integrated circuit processing. Inparticular, a balance between high packing density and yield require afinely tuned manufacturing process. Second order effects that might havebeen ignored a decade ago are now critical to cost-effective processingas will be explained in detail.

FIG. 1A is a schematic diagram of a 1T-1C ferroelectric random accessmemory (FeRAM) cell of the prior art. The memory cell includes an accesstransistor 108 coupled between a bit line 110 and a ferroelectriccapacitor 104. The ferroelectric capacitor 104 is coupled betweenstorage node 102 and a plate voltage (V_(P)) terminal 150. FIG. 1B is across sectional view of the ferroelectric memory cell of FIG. 1A asdisclosed by copending application Ser. No. 11/756,372, filed May 31,2007, and incorporated by reference herein in its entirety. Commonidentification numerals are used in multiple figures to indicate thesame features. The memory cell includes N-channel access transistor 108formed on P-substrate 120 having sidewall spacers 126 adjacent the gateregion. Source/drain region 110 is connected to a bit line terminal.Source drain region 102 is connected to the storage node. Isolationregion 122 separates the memory cell from adjacent memory cells in thememory array. A first dielectric region 130 overlies the accesstransistor 108. A contact region (CONT) 128 is formed in the dielectricregion 130 to electrically connect one plate 140 of ferroelectriccapacitor 104 to the storage node 102.

The ferroelectric capacitor 104 is a composite stack formed in layersand etched with a single mask step. The lower plate 140 is preferablyformed of titanium aluminum nitride (TiAlN) in conductive contact withiridium layer 142. Likewise, the upper plate 148 is preferably formed oftitanium aluminum nitride (TiAlN) in conductive contact with iridiumlayer 146. The upper and lower plates are separated by ferroelectriclayer 144. The ferroelectric layer 144 is preferably formed of leadzirconate titanate (PZT) or strontium bismuth tantalite (SBT). A seconddielectric region 160 overlies the ferroelectric capacitor 104. Platevoltage lead (MET1) 150 is formed on this second dielectric region andconnected to the top plate 148 of the ferroelectric capacitor 104 by afirst via region (VIA0). In areas of the semiconductor memory wherethere are no memory cells, VIA0 may directly contact CONT toelectrically connect MET1 to underlying gate or source/drain regions.

A significant problem disclosed in the prior art involves re-depositionof noble metal components (e.g. Pt, Pd, Ag, Au, Ir) on the sidewalls ofthe ferroelectric capacitor 104 during plasma etch. Such re-depositionmay cause the ferroelectric capacitor to leak or even completely shortthe upper and lower plates, thereby reducing the overall yield of thesemiconductor memory device. The prior art discloses a significant yieldimprovement is possible by controlling the sidewall slope of theferroelectric capacitor to a range of 78° to 88° with respect to thesurface of dielectric layer 130. This sidewall slope advantageouslyreduces the re-deposition of noble metal components without asignificant reduction of area of the ferroelectric capacitor 104. Thepresent inventors have discovered other factors that influencere-deposition of noble metal components on sidewalk of the ferroelectriccapacitor 104 as will be discussed in detail. There is therefore a needto further improve the method of forming ferroelectric capacitors.

BRIEF SUMMARY OF THE INVENTION

In a preferred embodiment of the present invention, a method of placinga dummy fill layer on a substrate is disclosed. The method includesidentifying a sub-region of the substrate. A density of a layer in thesub-region is determined. A pattern of a dummy fill layer is selected toproduce a predetermined density of the layer in the sub-region. Thedummy fill layer pattern is then placed in the sub-region. Local dummylayer fill patterns in a sub-region may be varied based on globaldensity to achieve a repeatable overall density through an iterativeprocedure. The resulting uniform and repeatable layer density improveslocal uniformity and device to device repeatability of a densitydependent semiconductor process.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1A is a schematic diagram of a 1-1C ferroelectric random accessmemory (FeRAM) cell of the prior art;

FIG. 1B is a cross sectional view of the FeRAM memory cell of FIG. 1A;

FIG. 2 is a flow chart of a dummy layer fill process of the presentinvention;

FIGS. 3A-3D are diagrams of a portion of a semiconductor integratedcircuit showing the dummy layer fill process according to the flow chartof FIG. 2;

FIGS. 4A-4C are extracted dummy layer fill patterns having differentdensities;

FIG. 5 is a table showing extracted dummy layer fill pattern density asa function of block layer density and drawn layer density;

FIG. 6 is a table showing a simplified extracted dummy layer fillpattern density as a function of block layer density and drawn layerdensity;

FIG. 7 is a flow chart of another embodiment of a dummy layer fillprocess of the present invention; and

FIG. 8 is a flow chart of yet another embodiment of a dummy layer fillprocess of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The preferred embodiments of the present invention provide significantadvantages in plasma etch stability for a given process over multipledesigns as will become evident from the following detailed description.

The present inventors have determined that different designs using thesame process flow may have significantly different yields. A primaryreason for this anomaly is the different layer densities on differentdesigns. In particular, the ferroelectric capacitor 104 of the memorycell (FIG. 1B) will etch at different rates for different memoryconfigurations on different designs. This is because different densitiesof the etched layer react differently during the plasma etch process.This phenomenon is common to all layers of the semiconductor deviceincluding polycrystalline silicon, dielectric layers, and metalinterconnect. Sensitivity of the ferroelectric capacitor to etch ratevariation, however, is greater than other layers due to re-deposition ofnoble metal components on the sidewalk as previously discussed. Thepresent inventors have determined that yield may begin to degrade withas little as +/−2% global variation of layer density. Thus, a variationof layer density of less than +/−10% at local areas near criticalcircuit components in the die as well as over the global wafer area ishighly desirable. The present invention is directed to a method ofcreating an adjustable dummy layer fill pattern during patterngeneration (PG) to make the layer density more uniform from a local aswell as a global perspective. The extracted dummy layer fill pattern isadded to the mask reticle together with the drawn layer pattern andsubsequently transferred to the semiconductor device. The density of asensitive layer such as the ferroelectric capacitor, therefore, will beapproximately the same for any design or memory configuration.

in the following discussion it should be understood that formation ofthe dummy layer fill pattern on a substrate refers to the pattern on theprocessing reticle as well as to the semiconductor substrate whichsubsequently receives the pattern. Moreover, it should be understoodthat a drawn layer is drawn by a circuit designer. Alternatively, anextracted layer is generally formed at PG as a function of the drawnlayer and may not be an electrically functional part of the circuit.

Turning now to FIG. 2, there is a flow chart illustrating the method ofcreating and placing a dummy layer fill pattern. The method will beexplained in detail with reference to FIGS. 3A-3D. Both global and localtarget layer densities are determined at step 200. The target layerdensity is a ratio of layer area to total area of a given region. Thetarget layer density is preferably comparable to the density of thelayer in the memory array and immediate periphery. The etch processparameters, including gas type, flow rate, source power, bias power, andetch time are preferably optimized for such critical layer geometries inthe memory array. For the purpose of the following discussion, it willbe assumed that the global and local target layer densities are 36%.Blocking areas of the pattern are identified at step 202. These blockingareas are regions of the where the dummy fill layer is prohibited.Recall from the discussion of FIG. 1B that layer VIA0 is electricallyconnected to layer CONT in the absence of the ferroelectric capacitor(FeCAP) layer. In this manner, the first metal layer (MET1) is connectedto underlying polycrystalline and source/drain regions of the die. Anyregion of the pattern, therefore, that includes drawn FeCAP, VIA0, orCONT layers or a required spacing from these layers is a blocking area.At step 204, the die pattern is partitioned into sub-regions. The sizeof these sub-regions is arbitrary and may be, for example, 100 μm by 100μm. The size should be small enough to maintain uniform local density ofthe dummy layer and large enough to produce a manageable number ofsub-regions. Multi-step identification of dummy layer regions isperformed at step 206. Step 206 is expanded in the flow chart on theright of FIG. 2.

Step 210 of multi-step identification begins with a first sub-region andsequentially steps through all sub-regions. Referring now to FIG. 3A,there is a simplified diagram of a sub-region 300 of the pattern. Thesub-region includes blocking areas 302, 304, and 308, having shaded CONTand VIA0 layers as well as a required minimum space from these layers.The density of each blocking area is a ratio of each blocking area tothe total area of the sub-region 300 as a percentage. Thus, blockingareas 302, 304, and 308 have densities of 4.3%, 11.4%, and 7.4%,respectively, for a total blocking area density of 26.8%. Additionally,area 306 includes four shaded FeCAP geometries for a layer density of3.7%. Both the blocking area density (BLOCK %) and the FeCAP layerdensity (FECAP %) are calculated at step 212. Referring next to FIG. 3B,dummy fill areas 310 and 312 are calculated as an inverse of areas 302through 308. At step 214 the dummy layer region is partitioned intosmaller areas. This produces simplified areas more closely approximatingrectangles and eliminates complex areas having internal voids. FIG. 3Cillustrates the result of partitioning the dummy layer region at step214. Area 320 is already sufficiently small so that no further divisionis necessary. Area 320, therefore, is accepted without furtherpartitioning. Area 312, however, is partitioned into areas 322 through332.

At step 216 a sub-region pattern density is selected. Although the fillpattern is arbitrary, the present inventors have selected squaregeometries having offset centers as represented at FIGS. 4A through 4Cfor a preferred embodiment of the present invention. Here, FIG. 4A hasthe greatest density and FIG. 4C has the least density. The dummy layerfill pattern density is selected from the table at FIG. 5. Table entriesof FIG. 5 are desired dummy layer fill pattern densities as a functionof BLOCK % and FECAP % densities. The BLOCK % density columns range from5% to 95%. The FECAP % layer density rows range from 0% to 35%. Forexample, if a sub-region has no FeCAP layer the dummy layer fill patterndensity is taken from the 0% row. If the BLOCK % is 5%, then 95% of thesub-region should receive a dummy layer pattern having a 38% density.This produces a FeCAP layer density in the sub-region of 0.95*38%=36.1%,which is close to the 36% target layer density. Similarly, if the BLOCK% is 35%, then 65% of the sub-region should receive a dummy layerpattern having a 55% density. This produces a FeCAP layer density in thesub-region of 0.65*55%=35.75%, which is also close to the 36% targetlayer density.

When a sub-region includes a FeCAP drawn layer, it must also be includedin the calculation. For example, if the sub-region includes a FeCAPdrawn layer having a 20% density, the dummy layer fill pattern densityis taken from the 20% row. If the BLOCK % is 15%, then 85% of thesub-region should receive a dummy layer pattern having a 19% density.This produces a FeCAP layer density in the sub-region of 0.85*19%+20% or36.15%. Similarly, if the BLOCK % is 45%, then 55% of the sub-regionshould receive a dummy layer pattern having a 29% density. This producesa FeCAP layer density in the sub-region of 0.55*29%+20%=35.95%.

Recall that the BLOCK % and FeCAP % densities from FIG. 3A are 26.8% and3.7%, respectively. The pattern density for FIG. 3A, therefore, isselected from the third column (25%) of BLOCK % and the second row (5%)of layer density. These tabulated values are nearest to the calculatedvalues. Thus, a dummy layer pattern density of 41% is used to fill areas320 through 332. This will produce a pattern density of approximately0.732*41%+3.7%=33.7%. This is 2.3% below the selected target layerdensity of 36%. However, subsequent sub-region density calculations willproduce an average dummy layer pattern density that approaches 36%. Ifthere are remaining sub-regions at step 218, control is transferred tostep 210, and the multi-step identification is repeated. Alternatively,when all sub-regions are associated with a respective pattern density,control transfers to step 220 to determine if the global target layerdensity is achieved. If the global density target is not achieved, a newlocal target layer density is selected at step 222. Then various localfill pattern densities are either increased or decreased to betterachieve the target global density. Control is then transferred to block210 and the process is then repeated until the global layer target isachieved. Once the global target layer density is achieved, controltransfers to step 208. At step 208, eligible areas of each sub-regionare filled with respective dummy fill patterns as shown at FIG. 3D toproduce a local and global target layer density of approximately 36%.

In one embodiment of the present invention, global layer density startsat either a maximum or minimum value and the fill process is repeatedwith progressively lower or higher local density fill patterns,respectively, until the global density target is achieved.

In another embodiment, global layer density starts at an intermediatevalue that may be arbitrary or determined by calculation based onblocking area size. Various local fill pattern densities are thenprogressively either increased or decreased based on the correspondingglobal layer density variation until the final global layer densitytarget is achieved. The resulting uniform density advantageouslyproduces repeatable etch rates locally and globally for multiple designsand memory configurations. Overall yield is significantly improved.

The table of FIG. 5 produces a near optimal fill density but requires 56different fill density patterns. Although this is well within theprocessing capability of the PG program, the number of fill patterns maybe reduced by taking advantage of the tendency to produce the targetfill density over a large number of sub-regions. Referring now to thetable of FIG. 6, the number of fill patterns is reduced from 56 (FIG. 5)to 5. Significant deviation from the target pattern density is notedwhere the BLOCK % is greater than 75%. This is because there isinsufficient unblocked sub-region area to reach the target patterndensity for any dummy layer pattern density. Even with such deviation,however, the global pattern density advantageously tends toward thetarget pattern density with acceptable deviation in the local patterndensity. As a result, yield is greatly improved and computationalcomplexity is reduced.

Turning now to FIG. 7, there is a flow chart illustrating anotherembodiment of the present invention. As previously described with regardto FIG. 2, both global and local target layer densities are determinedat step 200, and blocking areas of the pattern are identified at step202. At step 700 the die is partitioned into sub-regions based onblocking layer density. For example, blocking layer density ear thememory array will be near the target density. In this case, only a smallarea of dummy layer fill will be required. This small area is notcomputationally difficult and may, therefore, use a single fill pattern.Blocking layer density in peripheral circuit areas, however, may beconsiderably less than the target density and may require moreaggressive dummy fill patterns for each area. This may be accomplishedby reducing space between dummy fill geometries to near minimumpermitted by design rules. Finally, intermediate blocking area densityareas may require iterative dummy fill pattern computation as describedwith regard to FIG. 2. According to a preferred embodiment of thepresent invention, therefore, the die is partitioned into near targetdensity blocking regions, low density blocking regions, and at least oneintermediate blocking density region. At step 702, each of the neartarget density blocking regions and low density blocking regions arefilled with respective dummy fill patterns in a single step rather thanby iterative calculation.

Multi-step fill of remaining intermediate density blocking layer regionsproceeds at step 704 as shown in detail at the right. A first sub-regionis selected at step 710. As previously described with regard to FIG. 2,the both the blocking area density (BLOCK %) and the FeCAP layer density(FECAP %) are calculated at step 712. The selected sub-region is filledwith an initial dummy fill pattern. The dummy layer geometry size andspace are checked at step 716. This is similar to a design rule check asis known in the art. At step 718, the sub-region density is compared tothe global target density. If it is out of range, a new local targetdensity is selected at step 722 and control returns to step 714.Alternatively, if the sub-region density is within an acceptable range,a next sub-region is selected and control returns to step 710. Themulti-step fill operation of step 704 is repeated until all sub-regionsare filled. The embodiment of FIG. 7 advantageously reducescomputational complexity of the dummy layer fill procedure over FIG. 2by filling most of the die with fixed dummy fill patterns based onblocking layer density. Iterative dummy fill of remaining sub-regions islimited to 20% to 50% of the die.

Referring now to FIG. 8, there is a flow chart illustrating yet anotherembodiment of the present invention. As previously described with regardto FIG. 2, both global and local target layer densities are determinedat step 200, and blocking areas of the pattern are identified at step202. At step 800 a super cell list is generated. Each super cell is acell having other cells placed within it. This list is preferablyrelated to memory array cells, decode and sense amplifier logic, andperipheral logic having high, intermediate, and low blocking layerdensity. For example, the list may be generated by designers andfurnished to process engineers. At step 802, each super cell issubjected to iterative multi-step fill comparable to sub-region fill aspreviously described with regard to FIG. 7. An important difference isthat stepped or repeated cells may only require placement of a dummylayer fill pattern in one cell. This cell together with the calculateddummy layer fill pattern is then repeated as required.

Multi-step fill of the super cells proceeds at step 802 as shown indetail at the right. A first super cell is selected at step 810. Aspreviously described with regard to FIG. 2, the both the blocking areadensity (BLOCK %) and the FeCAP layer density (FECAP %) are calculatedat step 812. The selected super cell is filled with an initial dummyfill pattern. The dummy layer geometry size and space are checked atstep 816. This is similar to a design rule check as is known in the art.At step 818, the super cell density is compared to the global targetdensity. If it is out of range, a new local target density is selectedat step 822 and control returns to step 814. Alternatively, if the supercell density is within an acceptable range, a next super cell isselected and control returns to step 810. The multi-step fill operationof step 804 is repeated until all super cells are filled. The embodimentof FIG. 8 advantageously reduces computational complexity of the dummylayer fill procedure over FIG. 7 by iteratively filling super cells ofthe die with dummy fill patterns. The super cells are then repeated asrequired. The dummy fill layer for each super cell, therefore, is onlycalculated once.

Still further, while numerous examples have thus been provided, oneskilled in the art should recognize that various modifications,substitutions, or alterations may be made to the described embodimentswhile still falling with the inventive scope as defined by the followingclaims. Moreover, although a preferred embodiment of the presentinvention employs the flow chart of FIG. 2 to produce the dummy filllayer, the order of steps is not critical. For example, the order ofsteps 202 and 204 may be reversed. Step 214 reduces computationalcomplexity but is not strictly necessary. Finally, step 208 may beperformed for each sub-region during multi-step identification 206.Other combinations will be readily apparent to one of ordinary skill inthe art having access to the instant specification.

What is claimed is:
 1. A method of placing a dummy fill layer on a substrate, comprising: determining a global target layer density; identifying a plurality of sub-regions of the substrate; determining a local target density of a layer in each respective sub-region; selecting a first pattern of the dummy fill layer to place in a first of the plurality of sub-regions; and selecting a second pattern of the dummy fill layer to place in a second of the plurality of sub-regions.
 2. A method as in claim 1, comprising: identifying a blocking area of the substrate; and identifying the plurality of sub-regions of the substrate apart from the blocking area.
 3. A method as in claim 1, comprising: partitioning the substrate into plural subregions including the first and second sub-region; and determining a local target density of the layer in each respective sub-region.
 4. A method as in claim 1, wherein a final local target layer density of the first sub-region is within 10 percent of a final local target layer density of the second the sub-region.
 5. A method as in claim 1, wherein the first pattern of the dummy fill layer is placed in the first of the plurality of sub-regions in a single step.
 6. A method as in claim 1, wherein the second pattern is iteratively selected to produce a desired final local target layer density of the second sub-region. 